The present invention relates to hybrid power switching semiconductor devices which advantageously integrate an insulated-gate transistor (IGT), sometimes referred to in the past as an insulated-gate rectifier (IGR), and a power metal-oxide-semiconductor field-effect transistor (MOSFET). (A MOSFET may more generically be termed an insulated-gate field-effect transistor (IGFET), and the two terms, MOSFET and IGFET, are employed interchangeably herein.)
Various types of three-terminal power switching semiconductor devices are known. The various device types in many cases have different operating characteristics and are suitable for various different specific circuit applications. In efforts to advantageously combine their differing characteristics, circuits have ben proposed which include two discrete devices of different types, typically connected in parallel. As a convenient embodiment of such circuits, hybrid devices which integrate two difference device structures on a single semiconductor chip have also been proposed.
By way of pertinent example, an integrated MOSFET and bipolar junction transistor (BJT) switching device is disclosed in the following literature reference: N. Zommer, "The Monolithic HV BIPOS", paper number 11.5, IEDM 1981, pages 263-266. The device described by Zommer achieves in a single structure the relatively lower conduction losses of the bipolar junction transistor and the relatively higher speed and lower energy drive characteristics of a MOSFET. However, the integrated MOSFET and bipolar junction transistor device described by Zommer requires two different, yet synchronized, gate signals for the two parts of the device. Specifically, the MOSFET requires a voltage drive source for its gate and the bipolar junction transistor requires a current drive source for its base. Thus, the device is actually a four-terminal switching device requiring specialized gate drive signals. Additionally, different processing steps are typically employed for MOSFETs and bipolar junction transistors, so that fabricating a bipolar junction transistor and a MOSFET on the same chip is more difficult than fabricating either device alone.
To aid in understanding the present invention, it is helpful to review the structures and characteristics of power MOSFETs and IGTs, both of which are three-terminal semiconductor devices. MOSFETs are capable of relatively high-speed switching, but exhibit relatively low conductivity. IGTs exhibit relatively high conductivity (in the order of five times greater than bipolar junction transistor and twenty times greater than power MOSFETs), fast turn-on and the ability to withstand high time rate of change of current (di/dt) during turn-on, but relatively slow turn-off switching speed which restricts maximum operating frequency and can result in "current tailing", a condition in which the device is momentarily subjected to high current and high voltage simultaneously, with attendant high device power dissipation.
A typical N-channel power MOSFET includes an N+ (or highly-doped N conductivity type) source region and an N- (or high resistivity N conductivity type) drift or drain region separated from each other by a P base region having a channel surface. An insulated-gate electrode, typically formed of polysilicon, is disposed over the channel surface. In operation, application of a sufficiently large positive gate electrode bias (with reference to the source region) results in formation of an N conductivity type inversion layer in the P base region just below the channel surface. The inversion layer thus comprises an induced channel allowing conduction of electrical current between the source and drain. Examples of such devices are disclosed in Ishitani U.S. Pat. No. 4,072,975, and in Blanchard U.S. Pat. No. 4,145,703, to which reference may be had for further details.
MOSFETs are primarily unipolar conduction devices wherein primarily majority carrier (e.g. electron) current flows between source and drain. Excess charge carriers (electrons and holes) do not accumulate in the N drift region, permitting relatively rapid device turn-off. Thus, power MOSFETs are capable of relatively high switching speeds, in excess of 100 Mhz. Because current flow is limited by the majority carrier (electron) concentration in the N conductivity type induced channel and N conductivity type drift regions, the power MOSFET exhibits relatively high on-resistance. In MOSFETs designed for operation at greater than 100 volts, the resistance of the drift region becomes large because the majority carrier concentration in the drift region must be small and the drift region width must be large in order to support the device blocking voltages.
An IGT employs an insulated gate for controlling current flow between its main terminals, i.e., between its collector and emitter terminals. The gate and conduction channel of an IGT are structurally similar to corresponding elements of a MOSFET. Various forms of IGT devices are disclosed in commonly-assigned U.S. patent application Ser. No. 483,009, filed Apr. 7, 1983, a continuation of application Ser. No. 212,181, filed Dec. 2, 1980, by B. J. Baliga entitled "GATE ENHANCED RECTIFIER". (It may be noted that a "Gate Enchanced Rectifier", or "GERECT", is alternatively referred to herein as an "insulated-gate transistor", or "IGT". The two terms "GERECT" and "IGT" are intended to mean the same device.).
Previously-disclosed IGTs differ from vertical channel MOSFETs in that, in an N-channel IGT, a P+ collector region, not found in an N-channel MOSFET, is included, resulting in a four-layer, i.e., PNPN, device. Moreover, an IGT has relatively high di/dt capability, and much higher conductivity than a MOSFET. During forward conduction the P+ collector region of an IGT injects minority carriers (e.g. holes) into the N conductivity type base region corresponding to the drift region of a MOSFET. In the IGT, however, holes introduced into the N- base region from the IGT collector region recombine with electrons introduced from the IGT emitter, increasing device conductivity compared to a MOSFET.
The IGT does not turn off in an ideal manner when gate drive is removed, since excess majority carriers, e.g. electrons, tend to become trapped in the N-base region, so that the IGT continues conducting until the excess electrons are removed. Thus, while the IGT is turning off, high voltage and high current may occur simultaneously, resulting in high power dissipation in the device. While there are measures which may be taken to accelerate device turn-off and thus reduce turn-off power dissipation, in an IGT, such as providing emitter-to-base electrical shorts or by introducing recombination centers in the N base region to trap excess electrons, the present invention is concerned with alternative ways of avoiding high power dissipation during the IGT turn-off.